This Tuesday, Intel held an all-day virtual “Architecture Day” conference and took attendees on a deep dive into the architecture of upcoming products in all categories: CPUs, GPUs (dedicated and integrated), and FPGAs. We learned a lot about what Intel’s been working on and why, with the most concrete details being about the most imminent release—next month’s Tiger Lake laptop processors.
Ditching the ticks, tocks, and plusses
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“Be faster at everything, without using more power” is a pretty solid goal for a laptop CPU architecture.
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IBM’s Raja Koduri tells us about a transition from transistor-coupled to “transistor-resilient” design—meaning the ability to carry features from one process node to the next.
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Intel makes a case that their 10nm architecture is worth the wait, because it delivers more than simple density.
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We don’t often see CPU manufacturers bragging about individual transistors—but Intel spent much of the day doing exactly that.
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Intel says its new capacitors hold significantly more charge, while offering significantly less resistance—and therefore better power efficiency, with less heat.
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Intel combines their SuperMIM and Redefined FinFET technology buzzwords into a single buzzword to ditch the ++ terminology, calling the new process in Tiger Lake “SuperFin.”
Even for a conference called “Architecture Day,” Intel took us unusually deep into its manufacturing and packaging processes. The day’s presentations leaned as heavily on improvements in the individual transistors and capacitors on-die as they did on improvements in the processor designs themselves.
Aside from the purely educational angle, Intel’s focus on the lower levels of design appeared to serve two purposes. The lower-level focus made Intel’s 10nm process sound worth the unexpectedly long wait—and it gave Intel a chance to ditch the ponderous “++” suffixes to its process size and dub the whole thing a more human-friendly “SuperFin.”
With the 14nm process having hit “++++” and the 10nm already on “++,” even Intel’s own engineers were starting to get confused when talking to one another. So the change is good for more than just marketing. The SuperFin name is a portmanteau of “SuperMIM capacitor design” and “redesigned FinFET transistors.”
From micro to macro
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Willow Cove, the architecture Tiger Lake is built on, offers more cache, new security features, and significantly higher clock frequencies than Ice Lake.
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As voltage increases, so does maximum clockspeed. The Willow Cove architecture allows both lower and higher voltages than Sunny Cove did—and higher clocks at the same voltages, to boot.
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Say goodbye to “Iris” and “Iris+”, and say hello to Xe. Specifically, Xe LP—presumably Low Power—which is the iGPU architecture in Tiger Lake.
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Tiger Lake launches with LP-DDR4 support, but will eventually support LP-DDR5 RAM as well.
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Tiger Lake offers a more efficient Gaussian and Neural Accelerator, used for very low power inference tasks.
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Tiger Lake will have the ability to drive more, higher resolution displays than Ice Lake—and consume higher resolution imaging for AI workloads via its IPU6 pipeline, as well.
The problem with talking about the quality of individual transistors and capacitors in an overall package is that it’s difficult to translate directly to performance. So, now that we know Intel’s been working hard at the lower levels, we move on to design principles that are a little more familiar to most—voltages, frequencies, and subprocessors.
Tiger Lake is built upon Willow Cove, the microarchitecture which follows Ice Lake’s Sunny Cove. Willow Cove is billed as a significant improvement to Sunny Cove all the way around, with added security features, higher cache, and significantly improved clock speeds.
Willow Cove’s added clock speed doesn’t come with a power consumption handicap. Willow Cove processors have both a larger dynamic range and higher efficiency than Sunny Cove processors did—they can operate at both lower and higher voltages, and their frequencies (which scale with voltage) are higher at the same voltage as well.
We’re also looking forward to immensely improved integrated graphics. Ice Lake’s Iris+ was a much-needed shot in the arm for Intel’s traditionally wimpy iGPUs, but it still lagged significantly behind AMD’s Vega 11 integrated laptop graphics. Tiger Lake does away with Iris+ and introduces the much beefier Xe LP instead.
Intel describes its new line of Xe graphics, including Xe LP, as “industry leading”—and although the company isn’t talking benchmarks publicly yet, we suspect it’s not kidding. Leaked Time Spy benchmarks show a Tiger Lake i7-1165G7 beating AMD’s Ryzen 7 4700U on GPUs by a significant margin—35 percent of the raw score.
The same leaked benchmarks have the four-core / eight-thread i7-1165G7 and the 8c/8t Ryzen 7 4700U in a dead heat for CPU prowess, with effectively indistinguishable scores. It’s worth noting here that Time Spy is notoriously thread-limited—despite which the Ryzen 7 4800U, with eight cores and 16 threads, does beat the leaked i7-1165G7’s CPU score by 34 percent.
Finally, Tiger Lake will be able to drive more displays at higher resolutions—and handle AI workloads on larger resolution pipelines—than Ice Lake could.
Conclusions
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The TL;DR with all the micro-level improvements is a same-node performance jump as large or larger than a full node shrink.
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Intel is clearly well aware of the “meh” reaction to Ice Lake—and promising Tiger Lake will be anything but more of the same.
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The microarchitecture succeeding this year’s Willow Cove is next year’s Golden Cove—which will also come with a low-power (Atom/Celeron) microarchitecture called Gracemont, and a hybrid called Alder Lake.
We haven’t actually gotten our hands on any Tiger Lake parts yet, and there’s a world of difference between manufacturer claims and fully realized, independently tested systems. But Intel is practically oozing renewed confidence and making bold, if early, claims. It seems like a safe bet that Tiger Lake laptop CPUs will be serious competition for AMD’s Ryzen 4000—which neither Ice Lake nor Comet Lake really were.
The really interesting question—and one which Intel is still being cagey about—is how many Tiger Lake CPUs Intel will be able to supply to OEMs. The company’s presenters said that the 10nm supply problems we saw in Ice Lake had been “overcome”—but they didn’t give much definition of what that meant.
When we pressed Intel executives further, we received confirmation that there won’t be a repeat of Comet Lake—11th-generation mobile parts will be 10nm only, with no competing 14nm announcement. But that declaration came with some notably cautious hedges about what OEMs choose to buy and for how long. This could just be caution, or it could be an indication that Tiger Lake will only be seen in relatively low-volume, high-end systems in much the same way Ice Lake was.
https://arstechnica.com/?p=1697597